A memory device is typically comprised of memory cells arranged in an array of rows and columns, with each memory cell storing one or more bits of data. Memory cells within a given row of the array are connected to a common word line, while memory cells within a given column of the array are connected to a common bit line. Each of the memory cells in the array is coupled to a unique pair of a corresponding bit line and word line for selectively accessing the memory cell.
Traditionally, in the context of static random access memory (SRAM), six-transistor (6T) SRAM cells have been employed. Unlike dynamic random access memory (DRAM) cells, SRAM cells have the ability to hold data without requiring refreshing, and are therefore advantageous. However, as transistor geometries continue to shrink, it becomes increasingly more difficult to prevent local mismatch between the transistors forming the memory cells. This mismatch can adversely affect memory device performance, including, for example, the ability to consistently write data to the memory cells at low voltages (e.g., about one volt or less). To further exacerbate this problem, there has been a trend to reduce operating voltages of memory circuits, thereby reducing read and write margins of the SRAM cells which measure how reliably data can be read from and written to the SRAM cells, respectively. Due to the existence of static noise, among other factors, the reduced read and write margins may introduce errors in the respective read and write operations.